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23ECB301 VLSI Design

By Indumathi Categories: EEE, SNSCT

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Course Content

Syllabus

Syllabus

Lecture Notes

UNIT I – MOS TRANSISTOR PRINCIPLE
UNIT 1.1 CMOS fabrication – p-well process
UNIT 1.2 n-well process
UNIT 1.3 : TWIN TUB PROCESS3
UNIT 1.4 : MOS TRANSISTOR THEORY
UNIT 1.5 – IV CHARACTERISTICS
UNIT 1.6 – NON IDEAL IV EFFECTS
UNIT 1.7 – CMOS INVERTER – DC CHARACTERISTICS
UNIT II – COMBINATIONAL LOGIC CIRCUITS
UNIT 2.1- PROPAGATION DELAYS
UNIT 2.2 – STICK DIAGRAM
UNIT 2.3 – LAYOUT DIAGRAM
UNIT 2.4 – ELMORE’S CONSTANT
UNIT 2.5 – STATIC LOGIC GATES
UNIT 2.6 – PASS TRANSISTOR LOGIC
UNIT 2.7 – LOW POWER DESIGN PRINCIPLES
UNIT III – SEQUENTIAL LOGIC CIRCUITS
UNIT 3.1 – STATIC LATCHES AND REGISTERS
UNIT 3.2 – DYNAMIC LATCHES AND REGISTERS
UNIT 3.3 – PIPELINES
UNIT 3.4 – CLOCK STRATEGIES
UNIT 3.5 – LOW POWER MEMORY CIRCUITS
UNIT 3.6 – SYNCHRONOUS DESIGN
UNIT 3.7 – ASYNCHRONOUS DESIGN

Question Bank

UNIT I – MOS TRANSISTOR PRINCIPLE
UNIT II – COMBINATIONAL LOGIC CIRCUITS

Assignment

UNIT I – MOS TRANSISTOR PRINCIPLE

Puzzles

UNIT 1.1 – N-WELL PROCESS
UNIT 1.2- P-WELL PROCESS
UNIT 2- COMBINATIONAL LOGIC CIRCUITS
UNIT 3 – SEQUENTIAL LOGIC CIRCUITS

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Intermediate
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March 23, 2026 Last Updated
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