Old Website
Course Content
Syllabus
0/1
Syllabus
Lecture Notes
0/24
UNIT I – MOS TRANSISTOR PRINCIPLE
UNIT 1.1 CMOS fabrication – p-well process
UNIT 1.2 n-well process
UNIT 1.3 : TWIN TUB PROCESS3
UNIT 1.4 : MOS TRANSISTOR THEORY
UNIT 1.5 – IV CHARACTERISTICS
UNIT 1.6 – NON IDEAL IV EFFECTS
UNIT 1.7 – CMOS INVERTER – DC CHARACTERISTICS
UNIT II – COMBINATIONAL LOGIC CIRCUITS
UNIT 2.1- PROPAGATION DELAYS
UNIT 2.2 – STICK DIAGRAM
UNIT 2.3 – LAYOUT DIAGRAM
UNIT 2.4 – ELMORE’S CONSTANT
UNIT 2.5 – STATIC LOGIC GATES
UNIT 2.6 – PASS TRANSISTOR LOGIC
UNIT 2.7 – LOW POWER DESIGN PRINCIPLES
UNIT III – SEQUENTIAL LOGIC CIRCUITS
UNIT 3.1 – STATIC LATCHES AND REGISTERS
UNIT 3.2 – DYNAMIC LATCHES AND REGISTERS
UNIT 3.3 – PIPELINES
UNIT 3.4 – CLOCK STRATEGIES
UNIT 3.5 – LOW POWER MEMORY CIRCUITS
UNIT 3.6 – SYNCHRONOUS DESIGN
UNIT 3.7 – ASYNCHRONOUS DESIGN
Question Bank
0/2
UNIT I – MOS TRANSISTOR PRINCIPLE
UNIT II – COMBINATIONAL LOGIC CIRCUITS
Assignment
0/1
UNIT I – MOS TRANSISTOR PRINCIPLE
Puzzles
0/4
UNIT 1.1 – N-WELL PROCESS
UNIT 1.2- P-WELL PROCESS
UNIT 2- COMBINATIONAL LOGIC CIRCUITS
UNIT 3 – SEQUENTIAL LOGIC CIRCUITS
23ECB301 VLSI Design
Previous
Next
screen tagSupport

Report

Harassment or bullying behavior
Contains mature or sensitive content
Contains misleading or false information
Contains abusive or derogatory content
Contains spam, fake content or potential malware

Block Member?

Please confirm you want to block this member.

You will no longer be able to:

  • See blocked member's posts
  • Mention this member in posts
  • Invite this member to groups
  • Message this member
  • Add this member as a connection

Please note: This action will also remove this member from your connections and send a report to the site admin. Please allow a few minutes for this process to complete.

Report

You have already reported this .